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The future of computers: 3D chip stacking
- ot 15y agoWasn't that one of the innovations of Apple's A4 chip? Stacking the RAM chips on top of the CPU core inside the same package?
- abuzzooz 15y agoThe A4 does use this technology, but Apple certainly did not invent it (though I wouldn't be surprised if they claimed so). It has been used in cell phones for years, and only recently others are starting to adopt it, and extend it to place two chips side by side on a Si substrate within a single package. The reasons are purely economical. In the past, much benefit can be had just by shrinking the transistor size. At the current feature sizes, though, physics is not helping anymore and there is very little benefit in terms of raw transistor and wire speeds, and power. So chip makers need to find more ways to extend Moore's law a few more years. FinFETs and stacked chips are just such ways.
- wmf 15y agoTSV die stacking, wire-bond die stacking, and package-on-package chip stacking are different technologies with different costs and benefits. TSV stacking allows a massive number of wires between the layers, increasing bandwidth far beyond other types of stacking; of course, this comes at very high cost. Also, PoP stacking was used in mobile SoCs long before the A4.
- roc 15y ago> "chip stacking obviously works in synergy with Intel’s 3D FinFETs — though curiously there is no sign of TSV on Intel’s roadmap" Wouldn't chip stacking exacerbate heat dissipation issues? It seems to me that desktop chips would stand to gain far less from this approach, so why should it be surprising that Intel isn't rushing into it?
- IdahoEv 15y agoI wonder if you could etch channels for liquid coolant directly into every 3rd layer or so...
- wmf 15y agohttp://www.eetimes.com/electronics-news/4077160/IBM-GIT-demo-3D-die-with-microchannel-cooling http://www.eetimes.com/electronics-news/4077160/IBM-GIT-demo...
- cma 15y agoYou would reduce mean distance between all components and, depending on the graph of connections, save a lot on resistance losses.
- ippisl 15y agoBut what about servers ? memory bandwidth is the biggest problem facing servers, and stacking solves it nicely. And when you put chips side by side like xilinx's new chip, the heating issue is solvable.
- ksec 15y agoWe know this for a long time. Few years down the road in sub 10nm, we will reach the era where we cant shrink transistor endlessly. The problem with chip stacking on die is how to get rid of the heat passing through each layer. Stacking in itself has proven to be feasible by the Memory Cube. Where Heat isn't much of a concern.
- Symmetry 15y agoI expect that what we'll see is a top layers of general purpose processing on top next to the heat sinks, then lower power layers further down, like maybe a layer of L3 cache then a stack of main memory. Probably also a lot of dark silicon which is only lit up for special tasks, like media encoding or encryption.
- KeyBoardG 15y agoHasn't chip stacking been the future of computers for 10 years? Especially of SoC solutions.
- tcas 15y agoXilinx's Vertex 7 FPGA uses a stacked design for the interconnects. The FPGA logic is all 28nm, but sitting under it is a completely passive 65nm interconnect layer. http://www.xilinx.com/products/technology/stacked-silicon-interconnect/index.htm http://www.xilinx.com/products/technology/stacked-silicon-in...