For anyone confused by the HDL, it's the author's custom language: https://github.com/sylefeb/Silice/tree/master https://github.com/sylefeb/Silice/tree/master

For anyone confused by the HDL, it's the author's custom language: https://github.com/sylefeb/Silice/tree/master https://github.com/sylefeb/Silice/tree/master It provides a compiler to Verilog that then can be fed to traditional design flows.