3 ms·
Firrtl – Flexible Intermediate Representation for RTL
- peter_d_sherman 3y agoRelated: https://en.wikipedia.org/wiki/Register-transfer_level https://en.wikipedia.org/wiki/Register-transfer_level https://en.wikipedia.org/wiki/Verilog https://en.wikipedia.org/wiki/Verilog https://en.wikipedia.org/wiki/VHDL https://en.wikipedia.org/wiki/VHDL https://en.wikipedia.org/wiki/Chisel_(programming_language) https://en.wikipedia.org/wiki/Chisel_(programming_language) https://github.com/pymtl/pymtl3 https://github.com/pymtl/pymtl3 https://www.veripool.org/verilator/ https://www.veripool.org/verilator/ etc.