5 ms·
RISC-V has a whole HINT space that's basically just morphs of load immediate into zero register. AArch64 has a similar space: https://developer.arm.com/documen
by monocasa 3y ago
RISC-V has a whole HINT space that's basically just morphs of load immediate into zero register.
AArch64 has a similar space: https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/HINT--Hint-instruction- https://developer.arm.com/documentation/ddi0596/2020-12/Base...
And yes, PowerPC has a similar space as well holding hints like 'give priority to the other hardware threads on this core' and the like. https://utcc.utoronto.ca/~cks/space/blog/tech/PowerPCInstructionOddity https://utcc.utoronto.ca/~cks/space/blog/tech/PowerPCInstruc...
- rollcat 3y agoI was wondering where did I read about PowerPC, and this is exactly the article! So, it was for thread priority. Strikes me as an odd design choice, this probably should've been something to be managed by the OS more explicitly.
- monocasa 3y agoI think the idea of exposing it to user space is to better handle concurrency before trapping into the kernel. So consider the case of a standard mutex in the contended case. Normally the code will spin for a little bit before informing the kernel scheduler on the off chance that the thread that owns the lock is currently scheduled on another hardware thread. In that case it's in the best interest of the thread trying to grab the lock to shift most of the intracore priority to any other hardware threads so that it can potentially help the other hardware thread holding the lock get to a point where it gives up the lock quicker.