> The problem is that AVX-512 isn’t a singular instruction set. Different CPUs support different sets of AVX-512 instructions, meaning the instruction set on th

> The problem is that AVX-512 isn’t a singular instruction set. Different CPUs support different sets of AVX-512 instructions, meaning the instruction set on this AMD CPU might not match what our servers support anyway. Fortunately the common instructions are still useful. People tend to overstate the complexity of AVX-512 though. Chronological order of feature introduction isn't how the product was actually introduced, since client, server, and Xeon Phi have all followed their own independent development process. No product segment has ever regressed AVX feature support under Intel (other than the obvious rugpull at the end with Alder Lake). Alder Lake is a strict superset of Tiger Lake, Tiger Lake is a strict superset of Ice Lake, Ice Lake is a strict superset of Cannon Lake, Cannon Lake is a strict superset of Skylake-X. (Rocket Lake is technically Ice Lake/Sunny Cove backported to 14nm, and its direct product predecessor is Skylake-X not Tiger Lake, which never was officially released on desktop.) Sapphire Rapids is a strict superset of Cooper Lake, Cooper Lake is a strict superset of Cascade Lake, Cascade Lake is a strict superset of Skylake-X/Skylake-SP. For Xeon Phi, Knights Mill is a strict superset of Knights Landing. And you completely don't need to care about it unless your employer ends in "national labs". Again, the thing to remember is that dev teams at Intel have been very siloed for a long time, and between 10nm delays, 14nm capacity shortages, server delays, etc, it has been a long time since any of the product teams hit their chronological roadmaps. So the point in time when any product segment rolls out a uarch generation is very hit-or-miss (Golden Cove was 12th-gen/Alder Lake on desktop but is only releasing in Sapphire Rapids servers this year), and client and server are also diverging somewhat in featureset. (early 14nm didn't go well for Intel either - it's really been a rough decade for them, they have absolutely spun their wheels and barely managed to get product out the door for a long time now.) But there is never a case where you take a given server/client product segment and drop in the newer thing and regress a feature (up until the final rugpull with Alder Lake). It's just different progression levels of the "common core" as you advance through uarch generations/Coves, and then server/client having a few different things bolted on the sides (but they've never regressed these things). It's true though that AMD didn't quite do the same extensions as Intel either. But they're a lot closer to Alder Lake ("supports everything", until it didn't) than not. And this is simply part of developing a new standard - AMD had some with SSE4.x and 3DNow! that didn't pan out either. I did this chart a while ago based on taking the chronological ordering of the features and rearranging them based on the series they were introduced. Sapphire Rapids isn't quite right, it wasn't on the chart at the time so I added it, and it doesn't support VAES/VP2INTERSECT after all but you can see the monotonic capability progression pretty clearly. If you order it by product generation, it's way less intimidating than people make it. https://i.imgur.com/2HLrIjr.png https://i.imgur.com/2HLrIjr.png