4 ms·
Not entirely, but the process is very slow. RISC-V (and SiFive) caught a moment where it could be used is a way to squeeze ARM on pricing. It doesn't really me
by pclmulqdq 3y ago
Not entirely, but the process is very slow.
RISC-V (and SiFive) caught a moment where it could be used is a way to squeeze ARM on pricing. It doesn't really meaningfully create openness on the interesting parts of the stack (core architecture, SoC architecture, etc.) on its own. In that sense, the hype is overblown.
It does _enable_ open-source cores to some degree, but that's it, someone has to take the leap to make a production-ready one. A few companies are trying, but an open-source SoC is even further down the road.
- brucehoult 3y agoThe source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago. https://github.com/T-head-Semi/openc910 https://github.com/T-head-Semi/openc910 The same cores are used in the 64 core SG2042 workstation/server SoC.