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Wafer scale integration is a dead end technology. The engineering issues are just too great.

by skummetmaelk 3y ago

senttoschool 3y ago
Do you have a source?
- skummetmaelk 3y ago
  At high end production nodes it is impossible to get an entire wafer free of defects. Chips, let alone wafers, already include circuitry to disable parts of themselves if those parts have defects. Cerebras must have spent a ton of effort on getting this done for a full wafer. You also have problems like variability at the wafer level which you're less sensitive too when you put thousands of chips on a single wafer rather than just one, since they cover a smaller area. Look at how successful AMD's chiplet strategy has been. Chiplets sidestep the yield problems. Wafer scale amplifies them hundred or thousand fold. Nothing in the industry is designed to work with wafer scale products, so everything has to be custom made. Yes this is a chicken-egg problem, but it's going to be expensive to get any sort of momentum. The silicon industry is extremely conservative. It's sexy and enticing. If someone can make it work that's awesome. I will remain skeptical though.
  - cubefox 3y ago
    > Cerebras achieves 100% yield by designing a system in which any manufacturing defect can be bypassed – initially Cerebras had 1.5% extra cores to allow for defects, but we’ve since been told this was way too much as TSMC's process is so mature.
  - senttoschool 3y ago
    I'm well aware of chip defect rates and how they affect chips. >It's sexy and enticing. If someone can make it work that's awesome. I will remain skeptical though. But Cerebras has made it work since 2019 as @cubefox pointed out. They're on the second generation already and they have been shipping to customers for years. Here's a good overview of how they did it: https://www.anandtech.com/show/14758/hot-chips-31-live-blogs-cerebras-wafer-scale-deep-learning https://www.anandtech.com/show/14758/hot-chips-31-live-blogs...

Wafer scale integration is a dead end technology. The engineering issues are just too great.

senttoschool 3y ago

Do you have a source?

skummetmaelk 3y ago
At high end production nodes it is impossible to get an entire wafer free of defects. Chips, let alone wafers, already include circuitry to disable parts of themselves if those parts have defects. Cerebras must have spent a ton of effort on getting this done for a full wafer. You also have problems like variability at the wafer level which you're less sensitive too when you put thousands of chips on a single wafer rather than just one, since they cover a smaller area. Look at how successful AMD's chiplet strategy has been. Chiplets sidestep the yield problems. Wafer scale amplifies them hundred or thousand fold. Nothing in the industry is designed to work with wafer scale products, so everything has to be custom made. Yes this is a chicken-egg problem, but it's going to be expensive to get any sort of momentum. The silicon industry is extremely conservative. It's sexy and enticing. If someone can make it work that's awesome. I will remain skeptical though.
- cubefox 3y ago
  > Cerebras achieves 100% yield by designing a system in which any manufacturing defect can be bypassed – initially Cerebras had 1.5% extra cores to allow for defects, but we’ve since been told this was way too much as TSMC's process is so mature.
- senttoschool 3y ago
  I'm well aware of chip defect rates and how they affect chips. >It's sexy and enticing. If someone can make it work that's awesome. I will remain skeptical though. But Cerebras has made it work since 2019 as @cubefox pointed out. They're on the second generation already and they have been shipping to customers for years. Here's a good overview of how they did it: https://www.anandtech.com/show/14758/hot-chips-31-live-blogs-cerebras-wafer-scale-deep-learning https://www.anandtech.com/show/14758/hot-chips-31-live-blogs...