Latency is limited to the amount of buffering that's present in the interface logic (on sides). In the case of regular DP, there's just a few FIFOs and pipeline

Latency is limited to the amount of buffering that's present in the interface logic (on sides). In the case of regular DP, there's just a few FIFOs and pipeline stages, so the latency is measured in nanoseconds. When using display stream compression (DSC), there's a buffer of 1 line, and a few FIFOs to handle rate control. At the resolution for which DSC is used (say, 4K/144Hz), the time to transmit a single line is around 3us. So that's the maximum additional latency you can expect.