The contribution of this paper is showing that given a hardware I/O test set, a Monte-Carlo type procedure can be used to iteratively construct a reasonably com

The contribution of this paper is showing that given a hardware I/O test set, a Monte-Carlo type procedure can be used to iteratively construct a reasonably compact Boolean circuit representation (by manipulating BDDs). The toy example in the paper is an 8-bit adder. So given many examples of 8-bit addition, their procedure constructs a possible logic circuit for it. Then they still have to pass it onto standard logic synthesis tools. The RISC CPU example is the same, which means the resulting logic is not even a pipelined design. There are NO microarchitectural design optimizations (the authors propose this as future work, somehow). So given the C++ simulation I/O test traces of some CPU design, it is possible to extract a logic circuit for it, one that is not blowing up exponentially--mainly because the proposed algorithm is enough to separate a control and data path (ALU)--but yet it does not give any consideration to architectural optimizations like pipelining, caches, or anything else in the standard CPU architecture book by Patterson & Hennessy. The main point is that something like this could be used to bridge a design specification to an unoptimized logic function, so this is purely "functional" as opposed to architectural. It's a step but does not reflect the rather grandiose title of the paper.