4 ms·
Doesn't seem to be any discussion of what the inputs and outputs actually are here, at least for the "coarse-grained" approach. Suspect there is some "scaffoldi
by dooglius 3y ago
Doesn't seem to be any discussion of what the inputs and outputs actually are here, at least for the "coarse-grained" approach. Suspect there is some "scaffolding" around e.g. register map and memory access, and the rest is essentially learning a map from (instruction, register input vals)->(register output val, control registers for memory access)
- brutusborn 3y agoFrom Fig. 1, sounds like they test against a set of expected input/output pairs based on the ISA document. So I’m guessing the input is the ISA and predefined components like gates and connections, and the output is the location of those components and a set of connection routes.