Disclaimer: I'm not am expert. For your first question, the instructions are documented on the Intel website[0]. Many instructions have Latency and Throughput

Disclaimer: I'm not am expert. For your first question, the instructions are documented on the Intel website[0]. Many instructions have Latency and Throughput figures, which indicate how many cycles they take to execute. These are not straightforward to interpret due to instruction pipelining. As for cache exhaustion, that depends on how quickly you consume more data from memory. It's worth noting that the registers are an entire cache line in width, and that Latency figures are given for the instructions that load from memory into the AVX registers. [0] https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512&ig_expand=50 https://www.intel.com/content/www/us/en/docs/intrinsics-guid...