>How long does place and route take? If you want to avoid 12 hours builds you have to use floorplanning, incremental synthesis/implementation, and dynamic func

>How long does place and route take? If you want to avoid 12 hours builds you have to use floorplanning, incremental synthesis/implementation, and dynamic function eXchange (swappable components). I've been able to incrementally change designs to the scale of ~50K LUTs (look up tables, 50K LUTs is a big change) in about 15 minutes of synthesis and P&R with the rest of the design locked. (The chip here is about 400x the size of a single 50K LUT change so I imagine you could have a 100 hour builds if not using floor-planning and partitioning)