You stated all the implications, there's not significantly more to cache coherence than what you discussed here. Well, there's significantly more if you're try

You stated all the implications, there's not significantly more to cache coherence than what you discussed here. Well, there's significantly more if you're trying to implement coherence as an architect, but for the software author that's pretty much it. Cache lines have a size, if you have a line that's shared between two cores they keep needing perform an eviction each time one of the cores takes exclusive control to perform a write to that cache line, this is slow, the end. If you want the definitive source for this stuff, the Intel Architecture SDM, Volume 3 Ch12 would be a place to start. Then the Intel Optimization manual, Ch 3.6/3.7, and the Ch 2.x.y chapters for the micro-architecture which will describe the cache layout