3 ms·
At least the problem seems correctable. The DRAM controller would need to have an upper bound on the amount of time it'll keep RAS selected for a single row.
by rwmj 3y ago
At least the problem seems correctable. The DRAM controller would need to have an upper bound on the amount of time it'll keep RAS selected for a single row. Might even be possible with a firmware update as I understand that DRAM training/control is a horror of fragile, poorly understood, closed source software.
Edit: So reading further on, this is covered in section 7.3 "Limiting the Maximum Row-Open Time"
- bcrl 3y agoUltimately the complexity of managing all these DRAM corner cases needs to be handled inside the DRAM itself as there's just no way for DRAM controllers to be revised to cope with every new and exciting DRAM hardware bug. Sadly, the DRAM vendors continue to get away with publishing specs for their hardware that the hardware doesn't meet. Once upon a time that would result in a recall.