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At the time Graviton 1 deployed in AWS (November 2018) there were only two RISC-V ASICs in the world (SiFive FE-310 and FU-540) and both were low-volume test ch
by brucehoult 3y ago
At the time Graviton 1 deployed in AWS (November 2018) there were only two RISC-V ASICs in the world (SiFive FE-310 and FU-540) and both were low-volume test chips with just CPU cores and some RAM and GPIO. No PCIe, no USB. Proof of concept only.
The base instruction set (RV64GC + priv 1.10) was only set in stone in July 2019.
And of course the Graviton project will have started in more like 2015 when RISC-V was a rapidly-iterating draft spec with no chips, just starting to transition from being a university research project to being managed by the RISC-V Foundation.
A lot has changed in the last 4 1/2 years. There are now RISC-V server chips that are better than Graviton 1 (A72-class, 64 cores vs 16), with much better ones in the pipeline.