+1 This is how it is for logic design using gates, and I believe that's not a coincidence. Finding the right optimum between parallel and deep for logic desig

+1 This is how it is for logic design using gates, and I believe that's not a coincidence. Finding the right optimum between parallel and deep for logic design is computationally intensive itself, hence it often comes down to experiencial learning. The latter implies potential use of machine learning for that optimization. And it contunues ... lived happily thereafter. :-)