(for those who are not RISCV people a 'hartid' is a cpu register unique to each core that identifies it) (to the implementer) it's worth noting that hartids ar

(for those who are not RISCV people a 'hartid' is a cpu register unique to each core that identifies it) (to the implementer) it's worth noting that hartids are not guaranteed to be contiguous - one is guaranteed to be 0 - the rest will all be different, bot not necessarily 0,1,2,3,4,5.... It's to handle things like this: Suppose I have a board with 4 CPU chips on it, each chip has N CPUs on it (N might be variable, sometimes it's 2, 3, 4 - might depend on yield or on which chips you chose to put on the board (the cheap 2 core version or the expensive 8 core one). Each chip has some pins that indicate what some of the upper bits of the hartid, internally the various CPUs within the chip will set some low bits of their hartids. If I'm a chip designer who wants to make 256 core chips I'll reserve 8 bits for the lower bits and route the external chip pins to bits above that. My point though don't depend on hartids being contiguous