I think the problem with FPGAs and systolic arrays is the same... heterogeneity of the hardware. You always end up with lumpy hardware that you have to optimize

I think the problem with FPGAs and systolic arrays is the same... heterogeneity of the hardware. You always end up with lumpy hardware that you have to optimize for. I favor a radically stupid approach... just make a huge array of 4 bit in, 4 bit out, LUTs in a cartesian grid, clocked 2 to phases like the colors of a chess board. This results in cells that are NOT Turing complete, but an array that clearly is. The delays going across this "bitgrid" are huge, but each and every cell is computing, unlike any existing system. You can trivially map things, you can route around bad cells, flip the programs in any direction, actually wall off bits to ensure only certain I/O for a given area of computation.