> I wonder if we'll see a similar instruction for 2 bits -> 2 bits? Could be useful! No, because the way all modern high-performance CPUs work implies that an

> I wonder if we'll see a similar instruction for 2 bits -> 2 bits? Could be useful! No, because the way all modern high-performance CPUs work implies that an instruction with two destinations cannot really be any faster than two instructions with a single destination. So you can implement 3 bits -> 2 bits with two VPTERNLOGDs and can't do any better than that for 2 -> 2.