The TLB is basically keyed by (address space, virtual address % granularity), or needs to be flushed entirely when switching between different views of the addr

The TLB is basically keyed by (address space, virtual address % granularity), or needs to be flushed entirely when switching between different views of the address space (e.g. switching between processes). Unless your address space is exactly the same, you're at least going to duplicate TLB contents. Leading to a lower hit rate. This isn't really an OS issue, more a hardware one, although potential hardware improvements would likely have to be explicitly utilized by operating systems. Note that the TLB issue is different from the data / instruction cache situation.