On their RISC-V Summit speech slides, they even compared the implementation (Ascalon) with where they expect Zen5 to be, providing similar performance at lower

On their RISC-V Summit speech slides, they even compared the implementation (Ascalon) with where they expect Zen5 to be, providing similar performance at lower power. In any event, I am hopeful they will deliver something strong on time for it to be competitive. Considering the backgrounds of the people involved, this looks likely.