> With your favoured ISA style you can't just put 4 or 8 checked overflow add instructions in a row and run them all in parallel because they all write to the s

> With your favoured ISA style you can't just put 4 or 8 checked overflow add instructions in a row and run them all in parallel because they all write to the same condition code flag. This can be implemented using traps, without flags. And RISC-V supports delayed exceptions, which makes the implementation easier. > In this example you can't write back the updated r0 value until you know whether the instruction traps of not. RISC-V supports delayed exceptions, so you actually can.