4 ms·
Personally, I think that when one of your instructions has a cycle count of 23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SA
by exmadscientist 3y ago
Personally, I think that when one of your instructions has a cycle count of
23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT cycles to execute
4 cycles to fetch next instruction
and when that instruction is one of your ISA's main reasons for existing, and the whole thing is designed to be programmed directly rather than compiled, that's pretty CISC to me. Even if most of the instructions available are your standard RISC stuff (or just the basics).
But this whole discussion is and has always been rather fuzzy, so it's something of a moot point.