3 ms·

We know that they are over 100 bits (which is not very RISCy) and not fixed length as some constants cause the instructions to take more than one cache slots. I

We know that they are over 100 bits (which is not very RISCy) and not fixed length as some constants cause the instructions to take more than one cache slots. IIRC they are also not necessarily load store.

fooblaster 3y ago
Any source on some of the details here? I'm interested to know more.
- gpderetta 3y ago
  Agner Fog optimization guides have some. Otherwise Intel own manuals.
- hovav 3y ago
  X. Ren et al., "I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches," in proc. ISCA 2021: https://cseweb.ucsd.edu/~tullsen/isca2021.pdf https://cseweb.ucsd.edu/~tullsen/isca2021.pdf