I think if you want to analyze this to the same level of pedantry as the original blog post, the thing people actually mean is: "x86 instructions decompose int

I think if you want to analyze this to the same level of pedantry as the original blog post, the thing people actually mean is: "x86 instructions decompose into operations that feel somewhat RISC-like" And this is pretty much true. The author of this piece somewhat fixates on RISC-V as the anointed version of "RISC-ness" when it really is just one expression of the idea. The whole RISC vs CISC distinction is pretty silly anyway, because there isn't really a clear criterion or dividing line (see ARM's "RISC" instruction set) that separates "RISC" from "CISC." They're basically just marketing terms for "my instructions are reasonably simple" (RISC) and "my instructions are reasonably expressive" (CISC).