3 ms·

I'd guess there are a few hiding in the corners of the processor world. Think ultra-low-power (TI MSP430?) or DSP (TI C2000?). (I've used both of those two exa

I'd guess there are a few hiding in the corners of the processor world. Think ultra-low-power (TI MSP430?) or DSP (TI C2000?). (I've used both of those two examples, but it's been a while, and I don't have any particular desire to crack open their architecture manuals to see how CISCy or RISCy they are. It's kind of an academic distinction anyway at this point.)

exmadscientist 3y ago
I thought of one! Recent ESP32 processors have a "ULP Coprocessor" for ultra-low-power operations. Its instruction set is... well... not very RISCy: https://docs.espressif.com/projects/esp-idf/en/v4.2/esp32/api-guides/ulp_instruction_set.html https://docs.espressif.com/projects/esp-idf/en/v4.2/esp32/ap... (Spoiler alert for the lazy: it has single instructions for ADC reads and I2C transactions and such. I don't think it gets more CISC than that!)
- phire 3y ago
  Eh... It's a load/store architecture with fixed size instruction and all instructions execute in 1 cycle (unless they stall due to IO) That makes it quite RISCy. The overpowered instructions are just because it's an IO processor, they don't do much work on the CPU core itself, just trigger an IO component.
  - exmadscientist 3y ago
    Personally, I think that when one of your instructions has a cycle count of 23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT cycles to execute 4 cycles to fetch next instruction and when that instruction is one of your ISA's main reasons for existing, and the whole thing is designed to be programmed directly rather than compiled, that's pretty CISC to me. Even if most of the instructions available are your standard RISC stuff (or just the basics). But this whole discussion is and has always been rather fuzzy, so it's something of a moot point.

3 ms·

I'd guess there are a few hiding in the corners of the processor world. Think ultra-low-power (TI MSP430?) or DSP (TI C2000?). (I've used both of those two exa

by exmadscientist 3y ago

exmadscientist 3y ago
I thought of one! Recent ESP32 processors have a "ULP Coprocessor" for ultra-low-power operations. Its instruction set is... well... not very RISCy: https://docs.espressif.com/projects/esp-idf/en/v4.2/esp32/api-guides/ulp_instruction_set.html https://docs.espressif.com/projects/esp-idf/en/v4.2/esp32/ap... (Spoiler alert for the lazy: it has single instructions for ADC reads and I2C transactions and such. I don't think it gets more CISC than that!)
- phire 3y ago
  Eh... It's a load/store architecture with fixed size instruction and all instructions execute in 1 cycle (unless they stall due to IO) That makes it quite RISCy. The overpowered instructions are just because it's an IO processor, they don't do much work on the CPU core itself, just trigger an IO component.
  - exmadscientist 3y ago
    Personally, I think that when one of your instructions has a cycle count of 23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT cycles to execute 4 cycles to fetch next instruction and when that instruction is one of your ISA's main reasons for existing, and the whole thing is designed to be programmed directly rather than compiled, that's pretty CISC to me. Even if most of the instructions available are your standard RISC stuff (or just the basics). But this whole discussion is and has always been rather fuzzy, so it's something of a moot point.