3 ms·
I'm not sure how you could write something like this without considering something like the micro op cache, which is present in all modern x86 and some arm proc
by fooblaster 3y ago
I'm not sure how you could write something like this without considering something like the micro op cache, which is present in all modern x86 and some arm processors. The micro op cache on x86 is effectively is the only way an x86 processor can get full ipc performance, and that's because it contains pre decoded instructions. We don't know the formats here, but we can guarantee that they are fixed length instructions and that they have branch instructions annotated. Yeah sure, these instructions have more complicated semantics than true risc instructions, but they have the most important part - fixed length. This makes it possible for 8-10 of them to be dispatched to the backend per cycle. In my mind, this definitely is the "legend" manifested.
- jabl 3y agoDo we know they are fixed length? They could e.g. use a table with offsets to instruction boundaries in the cache?
- gpderetta 3y agoWe know that they are over 100 bits (which is not very RISCy) and not fixed length as some constants cause the instructions to take more than one cache slots. IIRC they are also not necessarily load store.
- fooblaster 3y agoAny source on some of the details here? I'm interested to know more.