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If someone says x86 decodes to RISC internally, they might be getting at one of two different ideas: (1) RISC really is the fastest/best way for CPUs to operat
by adrianmonk 3y ago
If someone says x86 decodes to RISC internally, they might be getting at one of two different ideas:
(1) RISC really is the fastest/best way for CPUs to operate internally.
(2) x86 performance isn't held back (much) by its outmoded instruction set.
x86 architectures were for a while translating into effectively RISC but stopped doing it. Now internally they are less RISC-like. This suggests #1 is false and #2 is true.
They could if they want to (because they have) but they don't want to anymore. Presumably because it's not the best way to do it. Although I guess it could be slightly better but not worth the cost of translating.
- pclmulqdq 3y agoI think if you want to analyze this to the same level of pedantry as the original blog post, the thing people actually mean is: "x86 instructions decompose into operations that feel somewhat RISC-like" And this is pretty much true. The author of this piece somewhat fixates on RISC-V as the anointed version of "RISC-ness" when it really is just one expression of the idea. The whole RISC vs CISC distinction is pretty silly anyway, because there isn't really a clear criterion or dividing line (see ARM's "RISC" instruction set) that separates "RISC" from "CISC." They're basically just marketing terms for "my instructions are reasonably simple" (RISC) and "my instructions are reasonably expressive" (CISC).