There's an enormous stack of SW in the HW that's enabling "cheap" ASIC development at the cost of chip performance. There's probably as much room to optimize on

There's an enormous stack of SW in the HW that's enabling "cheap" ASIC development at the cost of chip performance. There's probably as much room to optimize on any given node as there are optimization opportunities for the SW on that part. Both SW and HW have been leaning on Moore's law a long time.