Some SoCs will let you directly/explicitly use the cache as (ostensibly secondary) RAM, remapping your configuration from [cpu] -- [cache] -- ram to

Some SoCs will let you directly/explicitly use the cache as (ostensibly secondary) RAM, remapping your configuration from [cpu] -- [cache] -- ram to [ cpu ] | | [cache] [ram] Here's TI's documentation on doing just that CC13x2/CC26x2 family of MCUs: [0]. In this case, it's a seemingly paltry 8K of "RAM" but that's a lot for microcontroller developers! In this configuration and for this particular MCU, the CPU will actually run at a reduced speed (60% of its norm), probably because it needs to synchronize directly against the RAM. If you were to use it in CaR-only mode (which I don't think TI exposes), i.e. with the cache being used instead of rather than in addition to any RAM, you probably wouldn't need to run at those reduced speeds (and might even be able to run at higher clock speeds!). [0]: https://software-dl.ti.com/simplelink/esd/simplelink_cc13x2_26x2_sdk/3.30.00.03/exports/docs/proprietary-rf/proprietary-rf-users-guide/proprietary-rf-guide/cache-as-ram.html https://software-dl.ti.com/simplelink/esd/simplelink_cc13x2_...