3 ms·

The problem is that nobody is willing to pay a x100 penalty for security for general purpose computing.

• renox 3y ago
  Even a very low penalty isn't something that the industry is willing to produce.. For example, the RISC-V is derived from the MIPS, the MIPS had some instruction to trap on integer overflow, it's a very minor penalty to have these instructions, and guess what? They haven't been included in RISC-V..
  • snvzz 3y ago
    RISC-V would not add instructions w/o a strong justification, as simplicity has value in itself, and RISC-V is very RISC in recognizing that. If it's not that frequent and it can be done with 2 instructions, it'd be quite hard to make the argument for a dedicated instruction.
    • renox 3y ago
      Except that as soon as you have two instructions instead of one, people starts talking about cache pressure and turns off the safety. Optional security == no security.
      • snvzz 3y ago
        By that same logic, you might as well run everything in M mode.