Typically failed transistors are identified by the DFT scan chain. After the logic is netlisted (meaning, they create a giant list of flops, gates, and the wire

Typically failed transistors are identified by the DFT scan chain. After the logic is netlisted (meaning, they create a giant list of flops, gates, and the wires that connect them), the DFT tooling adds additional inputs to each flop that let it be controlled by a sideband signal, as a giant shift register. So you can put the chip in DFT mode and set all the flops to a known pattern. Run the clock a few cycles and you know what state the chip should be in (because you can simulate it). So you scan that giant shift register back out and check for differences. This process is automated, and for a given chip you might have a few gigabytes of stimulus total, which can collectively identify a single failed transistor (and kick that part out of the batch). Now, I have no idea how you take a picture of a bad transistor. That's beyond me.