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Does Backside Power Delivery mean the silicon area of the chip will be placed upside down on the motherboard to ensure efficient heat dissipation? (Since the po

Does Backside Power Delivery mean the silicon area of the chip will be placed upside down on the motherboard to ensure efficient heat dissipation? (Since the power source will be on the opposite side compared to current day silicon) P.s. in case you never heard of BPD technology, https://semiengineering.com/challenges-in-backside-power-delivery/ https://semiengineering.com/challenges-in-backside-power-del... is also informative (thanks @rektide for the Anand link!) Edit: Relevant quote from TFA which somewhat answers the above question: > Of note, because the carrier wafer is on the signal side of the chip, this means it presents another layer of material between the transistors and the cooler. Intel’s techniques to improve heat transfer take this into account, but for PC enthusiasts accustomed to transistors at the top of their chip, this is going to be a significant change. TL;DR: No.

rektide 3y ago
Previously we were using flip chip where silicon was exposed. With backside power delivery, there's now wiring on both sides of the chip. The transistors are buried. The article discusses how debugging is harder since nothing is exposed, and how there's now more thermal resistance. Intel's implementation has other factors, as discussed in the Anandtech article. Normally there's a fairly thick silicon base underneath the transistor layer, but Intel polishes that away to nearly nothing after the frontside signal wire layers are put down (to make hooking up the backside power easier). That greatly reduced structural strength & is a somewhat taxing process, so before doing the polishing down, they put a carrier wafer atop the frontside signal wire layers, adding some structural strength. And there it stays. Which means now that the top of the chip has a carrier wafer just for structure. Then the signal wire layers. Then the transistor layer with a bunch of PowerVias also in it. Then the backside power layer. In the first sample chip, there's still a quite a few signal layers, 14, Vs 15 on other chips. Only down by 1. But better chip utilization and other benefits (ir droop). The backside is 4 layer. Maybe maybe the backside power delivery might have (or maybe could someday) greatly let them cut down on the number of wire layers, which are all now between the transistors & the heatsink. But not yet. So there's a significant number of layers of things burying the transistors now. None the less, the thermals here looked fine. It's a great article.
- bboygravity 3y ago
  They must have a way to reach and debug the signal layers, at least in the lab? If not, I would intuitively think this whole approach would fail?
  - lisper 3y ago
    Why do you think it's necessary to debug signal layers by physically connecting to them (other than the I/O pins of the chip)? The only time you would actually try to connect to a chip other than through the I/O pins is in an adversarial situation. You might want to read this: https://en.wikipedia.org/wiki/Design_for_testing https://en.wikipedia.org/wiki/Design_for_testing
    - louissan 3y ago
      Pentium 2 cartridge, double-sided in 3, 2 ... 1...
    - rcxdude 3y ago
      It's not usually necessary, but they do in fact have this capability and do use it for testing and failure analysis (I think it is mostly used for debugging fabrication issues, where physically seeing the construction of the chip is important). The other amazing thing they can do is some level of rework: creating or removing connections to test a change or hypothesis without the expensive process of making a new mask for that layer. There's a video from intel's testing lab where the leader brags he can take a chip with a single failed transistor somewhere in it, and give you a picture of it.
      - thrtythreeforty 3y ago
        Typically failed transistors are identified by the DFT scan chain. After the logic is netlisted (meaning, they create a giant list of flops, gates, and the wires that connect them), the DFT tooling adds additional inputs to each flop that let it be controlled by a sideband signal, as a giant shift register. So you can put the chip in DFT mode and set all the flops to a known pattern. Run the clock a few cycles and you know what state the chip should be in (because you can simulate it). So you scan that giant shift register back out and check for differences. This process is automated, and for a given chip you might have a few gigabytes of stimulus total, which can collectively identify a single failed transistor (and kick that part out of the batch). Now, I have no idea how you take a picture of a bad transistor. That's beyond me.
gumby 3y ago
> for PC enthusiasts accustomed to transistors at the top of their chip, this is going to be a significant change. Seriously? The chip is inside a carrier but enthusiasts care which side the transistors are on? Absurd.

rektide 3y ago

Previously we were using flip chip where silicon was exposed. With backside power delivery, there's now wiring on both sides of the chip. The transistors are buried. The article discusses how debugging is harder since nothing is exposed, and how there's now more thermal resistance. Intel's implementation has other factors, as discussed in the Anandtech article. Normally there's a fairly thick silicon base underneath the transistor layer, but Intel polishes that away to nearly nothing after the frontside signal wire layers are put down (to make hooking up the backside power easier). That greatly reduced structural strength & is a somewhat taxing process, so before doing the polishing down, they put a carrier wafer atop the frontside signal wire layers, adding some structural strength. And there it stays. Which means now that the top of the chip has a carrier wafer just for structure. Then the signal wire layers. Then the transistor layer with a bunch of PowerVias also in it. Then the backside power layer. In the first sample chip, there's still a quite a few signal layers, 14, Vs 15 on other chips. Only down by 1. But better chip utilization and other benefits (ir droop). The backside is 4 layer. Maybe maybe the backside power delivery might have (or maybe could someday) greatly let them cut down on the number of wire layers, which are all now between the transistors & the heatsink. But not yet. So there's a significant number of layers of things burying the transistors now. None the less, the thermals here looked fine. It's a great article.

bboygravity 3y ago
They must have a way to reach and debug the signal layers, at least in the lab? If not, I would intuitively think this whole approach would fail?
- lisper 3y ago
  Why do you think it's necessary to debug signal layers by physically connecting to them (other than the I/O pins of the chip)? The only time you would actually try to connect to a chip other than through the I/O pins is in an adversarial situation. You might want to read this: https://en.wikipedia.org/wiki/Design_for_testing https://en.wikipedia.org/wiki/Design_for_testing
  - louissan 3y ago
    Pentium 2 cartridge, double-sided in 3, 2 ... 1...
  - rcxdude 3y ago
    It's not usually necessary, but they do in fact have this capability and do use it for testing and failure analysis (I think it is mostly used for debugging fabrication issues, where physically seeing the construction of the chip is important). The other amazing thing they can do is some level of rework: creating or removing connections to test a change or hypothesis without the expensive process of making a new mask for that layer. There's a video from intel's testing lab where the leader brags he can take a chip with a single failed transistor somewhere in it, and give you a picture of it.
    - thrtythreeforty 3y ago
      Typically failed transistors are identified by the DFT scan chain. After the logic is netlisted (meaning, they create a giant list of flops, gates, and the wires that connect them), the DFT tooling adds additional inputs to each flop that let it be controlled by a sideband signal, as a giant shift register. So you can put the chip in DFT mode and set all the flops to a known pattern. Run the clock a few cycles and you know what state the chip should be in (because you can simulate it). So you scan that giant shift register back out and check for differences. This process is automated, and for a given chip you might have a few gigabytes of stimulus total, which can collectively identify a single failed transistor (and kick that part out of the batch). Now, I have no idea how you take a picture of a bad transistor. That's beyond me.

gumby 3y ago

> for PC enthusiasts accustomed to transistors at the top of their chip, this is going to be a significant change. Seriously? The chip is inside a carrier but enthusiasts care which side the transistors are on? Absurd.