What would be CISC-like is if the opcode operated on memory locations, such that the CPU would have to deal with it taking a page fault. Anyway, here's John Ma

What would be CISC-like is if the opcode operated on memory locations, such that the CPU would have to deal with it taking a page fault. Anyway, here's John Mashey, who helped design the MIPS, on RISC v CISC: https://yarchive.net/comp/risc_definition.html https://yarchive.net/comp/risc_definition.html