As far as I know, this is already hardware that implements this. [0] > […] It is because of a special feature of the U74 that when it sees a short forward bran

As far as I know, this is already hardware that implements this. [0] > […] It is because of a special feature of the U74 that when it sees a short forward branch over exactly one ALU instruction it pairs the two instructions together in the A and B pipelines and instead of predicting whether the branch in the A pipe is taken or not it uses the result of the comparison to predicate the instruction in the B pipe. > It turns it into a NOP at the last moment, or doesn't write the result back to the destination register or something like that. Also note that the compressed relative branch instructions only use 16 bytes to encode. [0] https://www.reddit.com/r/RISCV/comments/132s19s/hand_optimised_riscv_assembly_language_clz/ https://www.reddit.com/r/RISCV/comments/132s19s/hand_optimis...