3 ms·

Interestingly, the CPU core used in this seems to have some undocumented instructions that are not present on Intel/AMD (and conflict with SALC there, though th

Interestingly, the CPU core used in this seems to have some undocumented instructions that are not present on Intel/AMD (and conflict with SALC there, though this shouldn't be a problem, since it is also an undocumented opcode and rarely ever used). The linked datasheet only lists a few of those, and it seems there is not even enough information there on how SMM should be implemented: it says that CR0, EFLAGS, EIP and the CS descriptor are saved/restored using some internal registers, and that the SMM code is responsible for everything else - without explaining how exactly to do this. F1 enter SMM (ICEBP) D6 E6 exit from SMM D6 CA 03 A0 load SMM entry point register with EAX D6 C8 03 A0 load EAX with SMM entry point??? D6 FA 03 02 load power control register with EAX

userbinator 3y ago
It's called HSM and seems to be described starting around page 31 here: https://www.dmp.com.tw/app/webcamera/pdf/m6117d.pdf https://www.dmp.com.tw/app/webcamera/pdf/m6117d.pdf
- rep_lodsb 3y ago
  Yes, but pretty much all the information about how the "M1386SX" core handles SMM is contained on that single page, the following ones only describe I/O ports. And it leaves a lot of questions unanswered, like how to access the "GR" registers (something like MSRs on Pentium+?), or the other descriptor caches that aren't saved automatically. The text is written as if these were standard features of the architecture, or at least documented elsewhere (maybe they were, but can't find anything online now).