38 ms·

OT but a question I'm curious about: what features would people who have a lot of experience with the RP2040 like to see on a successor?

cdcarter 3y ago
Another pair of PIO blocks (and two more DMA channels) is my desire. I think a lot of people would love to see a (slightly more expensive) variant with more uncommitted GPIOs. My pet projects with the Pico and clones involve interfacing with an 8-bit processor, and the RP2040 just doesn’t expose enough pins for the full data, address, and control busses AND actually doing something interesting with the outside world. Another dedicated USB PHY peripheral would also be great, a lot of people lose a PIO block to adding a second USB port. Obviously this also shows the power of PIO, but it’s nice to be able to reserve those blocks for more obscure physical things. I bet a lot of people would like more analog pins, the Teensy provides a lot more, for example.
happycube 3y ago
I haven't done a lot per se, but 480Mb USB would be nice.
- deleted 3y ago
  [deleted]
- duskwuff 3y ago
  USBHS is fairly hard to support without an off-chip transceiver. There's a reason why most low-cost microcontrollers are USBFS only.
vardump 3y ago
Memory mappable PSRAM support would be nice. Or more pins and more PIO as well. I guess more SRAM wouldn't hurt either.
polpo 3y ago
More than 32 instructions per PIO block: my main current project (PicoGUS) uses 32 instructions on one PIO block and 31 on the other to handle ISA IO, ISA DMA, I2S audio out, and SPI PSRAM access. Having more would let me cut a few less corners in how ISA is handled. More/more flexible PIO instructions: branching is very limited, you can only arbitrarily SET up to 5 pins or pindirs at once (increasing to 8 would be a godsend), stalling with a sideset repeatedly executes the sideset, etc... I could go on. Memory mapped PSRAM: I made a library to assist with accessing SPI PSRAM but it's still just functions to get/set groups of bytes. An intelligent cache around it would also mitigate the much higher latency of accessing PSRAM as well. More SRAM: everyone can always use more RAM! More GPIOs: everyone can always use more GPIOs!
CarVac 3y ago
One more core, one more PIO, and more SRAM.
mtreis86 3y ago
Better power consumption, especially in deep sleep. Make waking up cheap too, especially for some IOT purposes, like grabbing a sensor reading every couple minutes and storing it in a queue for future burst transmission. Optimize for that sorta thing. Measure in nanoamps.
claxo 3y ago
A DAC, at least 12 bits

cdcarter 3y ago

Another pair of PIO blocks (and two more DMA channels) is my desire. I think a lot of people would love to see a (slightly more expensive) variant with more uncommitted GPIOs. My pet projects with the Pico and clones involve interfacing with an 8-bit processor, and the RP2040 just doesn’t expose enough pins for the full data, address, and control busses AND actually doing something interesting with the outside world. Another dedicated USB PHY peripheral would also be great, a lot of people lose a PIO block to adding a second USB port. Obviously this also shows the power of PIO, but it’s nice to be able to reserve those blocks for more obscure physical things. I bet a lot of people would like more analog pins, the Teensy provides a lot more, for example.

happycube 3y ago

I haven't done a lot per se, but 480Mb USB would be nice.

deleted 3y ago
[deleted]
duskwuff 3y ago
USBHS is fairly hard to support without an off-chip transceiver. There's a reason why most low-cost microcontrollers are USBFS only.

vardump 3y ago

Memory mappable PSRAM support would be nice. Or more pins and more PIO as well. I guess more SRAM wouldn't hurt either.

polpo 3y ago

More than 32 instructions per PIO block: my main current project (PicoGUS) uses 32 instructions on one PIO block and 31 on the other to handle ISA IO, ISA DMA, I2S audio out, and SPI PSRAM access. Having more would let me cut a few less corners in how ISA is handled. More/more flexible PIO instructions: branching is very limited, you can only arbitrarily SET up to 5 pins or pindirs at once (increasing to 8 would be a godsend), stalling with a sideset repeatedly executes the sideset, etc... I could go on. Memory mapped PSRAM: I made a library to assist with accessing SPI PSRAM but it's still just functions to get/set groups of bytes. An intelligent cache around it would also mitigate the much higher latency of accessing PSRAM as well. More SRAM: everyone can always use more RAM! More GPIOs: everyone can always use more GPIOs!

CarVac 3y ago

One more core, one more PIO, and more SRAM.

mtreis86 3y ago

Better power consumption, especially in deep sleep. Make waking up cheap too, especially for some IOT purposes, like grabbing a sensor reading every couple minutes and storing it in a queue for future burst transmission. Optimize for that sorta thing. Measure in nanoamps.

claxo 3y ago

A DAC, at least 12 bits