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I thought I was crazy when looking at all those vector extensions piling up made me think "why not just have some generic-sized vector instructions, and then le
by Joker_vD 3y ago
I thought I was crazy when looking at all those vector extensions piling up made me think "why not just have some generic-sized vector instructions, and then let the CPU to sort out what is the largest chunk size it actually supports internally" but apparently no, I am not! It was actually been done before and we might even have that again in the future. That's nice.
- r3ndr 3y agoARM's newer SVE/SVE2 instructions can do something like this now. SVE allows the vector length to vary between 128 and 2048 bits, at 128 bit increments. RISC-V's vector RVV instructions also allow the vector length to vary across different CPU implementations. This way, the same RVV vector code can run on different CPUs having different vector lengths.