No, classic Cray did have a fixed vector size (4096 bits, or 64 double precision floating point values) both in the HW and the ISA. What it did have, however, w

No, classic Cray did have a fixed vector size (4096 bits, or 64 double precision floating point values) both in the HW and the ISA. What it did have, however, which most contemporary SIMD ISA's lack, was a vector length register which allowed masking the end of the vector register. That meant the compiler didn't have to generate a scalar loop tail to handle the final iterations of a vectorized loop, it just set the vector length register to mask of the end of the vector data register, which meant that load/store/arithmetic instructions only worked on the first N elements in the vector rather than the full 64. I think the RISC-V V extension, as well as ARM SVE, both have something similar as well. What RVV and SVE have, that Cray vector ISA didn't, is the ability to support different HW vector register lengths with the same ISA.