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I'm also curious if Apple SoCs' storage controllers have some fancy error-checking, along with AES.
by sillywalk 3y ago
I'm also curious if Apple SoCs' storage controllers have some fancy error-checking, along with AES.
- ryao 3y agoAs far as I know, Apple has the NAND controller integrated into the SoC. The NAND controller needs to have ECC to keep the error rates on flash down to something acceptable.
- sillywalk 3y agoThat was sort of what I was wondering, if the NAND controller has some extra Apple Stuff(tm) beyond standard ECC.
- Eric_WVGG 3y agoI'm pretty sure that is the reason why support for Fusion Drives was abruptly ganked and punted out by a year.
- daniel-cussen 3y ago[dead]
- wtallis 3y agoThe standard for SSDs goes far beyond the ECC used on DRAM. Every SSD controller designer will have their own proprietary scheme, often a simple and fast BCH that falls back on LDPC for higher error rates. The exact codeword sizes and other parameters of the codes are vendor-specific.