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I see RISC-V as a time bomb. These are known "detonators" set up for next year. There's more we don't even know of. It is going to happen. RISC-V is inevitabl
by snvzz 3y ago
I see RISC-V as a time bomb.
These are known "detonators" set up for next year. There's more we don't even know of. It is going to happen.
RISC-V is inevitable.
>As far as I know and specs wise
December 2021's batch of extensions done the magic. No hardware out there implements them.
Once it arrives (e.g. Veyron and Ascalon), the thorough disruption of the whole CPU landscape, from microcontrollers to supercomputers, starts.
The acceleration and massive momentum that we've seen to date is nothing compared to what's to come.
- sylware 3y agoI think this may be a bit too many instructions (I did not see hardware accelerated memcpy/memset though). I guess I would use only a small subset of them. Since RISC-V is a royalty free standard, writting directly assembly is worth it, until the abuse of a macro processor and code generation is avoided. I want to share you optimism, but I advise you to keep your cool. There is a long road to reach the performance of x86/arm microarchitectures (it is harder for risc-v since the "market is over saturated"). And those performant implementations must get access to the best silicium node process... and that...
- snvzz 3y agoVeyron and Ascalon's planned releases aren't "IP to license" releases, but actual chips. Veyron's supposed to have actual server boards on sale late this year. Ascalon, CPU chiplets and a full AI accelerator product using them, succeeding their current one, which iirc uses SiFive IP.