In university, we used individual macro components in Altera's tools (ModelSim/Quartus) to construct a microcoded, superscalar, pipelined CPU with branch predic

In university, we used individual macro components in Altera's tools (ModelSim/Quartus) to construct a microcoded, superscalar, pipelined CPU with branch prediction. It was way more painful than Verilog but had a "visual programming" UX to it. For a complete processor emulating the real world, there's OpenSPARC. https://www.oracle.com/servers/technologies/opensparc-t2-page.html https://www.oracle.com/servers/technologies/opensparc-t2-pag... I'm sure there are dozens of open core RISC-V implementations out there and maybe some ARM ones too.