4 ms·
Speaking from memory and coarse grained understanding, 1) MLC/TLC/QLC work more like 4/8/16-tone grayscale e-paper than flash: e.g. 0x10 = (1,0,1,0), that’s “4
by numpad0 3y ago
Speaking from memory and coarse grained understanding,
1) MLC/TLC/QLC work more like 4/8/16-tone grayscale e-paper than flash: e.g. 0x10 = (1,0,1,0), that’s “4 level/bits per cell”. And it’s not a single pulse of 0x10 voltage into a memory cell, more like repetitive pulses from 0b1111 to enough millivolts below 0b1011. Readout is probably more complicated, let alone lifecycle management. Those businesses might be more involved than it’s worth filesystem researchers time.
2) It was often said, at least years ago, that the considerable fraction of heat in NVMe SSDs comes from PCIe serialization/deserialization(SerDes), rather than payload data processing or NAND programming.
If both of above are true, maybe it’s PCIe that should be replaced, with something more like the original PCI?
- nine_k 3y agoThe original PCI was parallel. You can't have an excessively fast parallel bus, because the tiniest differences between lanes make different pins receive the signal out of sync. This is why RAM interface is so hard to get right, and the lanes there are as short as possible.