All that exist at the moment! i.e. - THead C906 in-order single-issue core in e.g. AllWinner D1 and Bouffalo BL808 SoCs - THead C910 3-wide OoO core in THead

All that exist at the moment! i.e. - THead C906 in-order single-issue core in e.g. AllWinner D1 and Bouffalo BL808 SoCs - THead C910 3-wide OoO core in THead TH1520 and Sophon SG2042 SoCs LMUL=4 (64 bytes per loop) is optimal for all the above. It is unlikely to be bad on anything. I look forward to the first shipping RVV 1.0 implementations, maybe sometime in 2024. The same code is binary compatible between RVV draft 0.7.1 (which the above implement) and the ratified RVV 1.0, and source compatible with the addition of ",ta,ma" to the `vsetvli` (sadly, a decision was made not to allow that to default in asm) As can be seen at... https://hoult.org/d1_memcpy.txt https://hoult.org/d1_memcpy.txt ... a test I ran on the Allwinner D1 two years ago. Compared to glibc memcpy() at the time, the vector version is 2-3 times faster for sizes up to 1k, then gradually slides back to equality at sizes in L2 cache and RAM where normal integer code can saturate the bus. That's a core (C906) which today is available on for example the $6 Pine64 Ox64 board.