4 ms·
Doesn’t PCIe already get you that today? Either with an existing PCIe -> X bridge chip, or an FPGA with PCIe capability? It’s not cheap, and you need to write
by bpye 3y ago
Doesn’t PCIe already get you that today? Either with an existing PCIe -> X bridge chip, or an FPGA with PCIe capability?
It’s not cheap, and you need to write device drivers etc - but that’s the case regardless.
- sfrigon 3y agoMaybe PCIe already does something similar, that's not something I have knowledge about. Though there is a small difference in my opinion, where, from the point of view of the CPU, it should behave as a normal interface, thus the driver should already exist, and only require a change in the device tree (for linux). It would still require quite a bit of work: - The PIO has to behave bug-for-bug compatible with an existing driver - The exposed pins need have the proper voltage levels & electrical protection .. but that's just fantasy for now.
- naikrovek 3y agosounds like PCIe, as mentioned. there are a few FPGA dev kits which are set up this way. I have one which has a dual core Atom CPU and a large FPGA connected via PCIe, and the speed is fast.