From what I can tell, they're not supporting them in virtualization. Instead, they're set up to cause processor traps, which the hypervisor could catch and use

From what I can tell, they're not supporting them in virtualization. Instead, they're set up to cause processor traps, which the hypervisor could catch and use to emulate those instructions if necessary. > ...and those modes are honestly not hard to support. I have to imagine that there's a decent amount of extra logic in the load/store units to use the current processor mode to work out memory semantics, and now I'm thinking about questions like "what would happen if one thread is in virtual 8086 mode while the hyperthread partner isn't". That's a noticeable burden in things like validation. And even if the implementation of segmentation is simpler than paging, that's not the issue; the issue is that it's a different pathway, and potentially one that cuts deep into the execution unit. If it's the sort of thing where eliminating support for anything other than paging means getting an L1 cache hit back one cycle faster... then sign me up.