3 ms·

For those truly too lazy to click through to the article, x86-S stands for "simplified," with the idea being to boot directly into 64-bit mode instead of bootin

by loeg 3y ago

For those truly too lazy to click through to the article, x86-S stands for "simplified," with the idea being to boot directly into 64-bit mode instead of booting into 16-bit and bootstrapping to 64-bit mode. 16-bit mode would be removed entirely. It's not clear to me if 32-bit mode would be axed as well, or if it would be retained (maybe partially).

KerrAvon 3y ago
The PDF goes into detail on this. tl;dr: > 16-bit and 32-bit protected mode are not supported anymore and cannot be entered. The CPU always operates in long mode. The 32-bit submode of Intel64 (compatibility mode) still exists.
- dathinab 3y ago
  Yes but there is a bit of a catcher due to some 32bit programs abusing certain instructions created for handling segmentation. And segmentation support will be partially removed. But no idea if the instruction in question will be gone.
  - anticensor 3y ago
    Removed instructions and pseudocode of changing instructions are explicitly documented.
aforty 3y ago
It seemed pretty obvious to me from one of the graphics that they would remove 32-bit mode as well.
- loeg 3y ago
  > It seemed pretty obvious to me from one of the graphics that they would remove 32-bit mode as well. I don't believe it's that simple (or obvious, since you seem to be mistaken).
- dathinab 3y ago
  If you mean the graphics relatively at the beginning then no, they refer to boot phases and OS level stuff but that's not fully the same as what you need to run 32bit applications in a 64bit OS.
jcranmer 3y ago
> It's not clear to me if 32-bit mode would be axed as well, or if it would be retained (maybe partially). I've been reading the detailed pdf to see more details. It looks to me like 32-bit mode, specifically in the sense of a 32-bit distribution of modern software, is being retained. Segments would be converted more towards their 64-bit extremely attenuated mode, rather than the more robust functionality they have right now. So most 32-bit software shouldn't be affected, unless you're getting really dirty with the segmentation features or trying to support something like Win16.
- peterfirefly 3y ago
  > Segments would be converted more towards their 64-bit extremely attenuated mode, rather than the more robust functionality they have right now. Which, ten years down the line, should free up a bit more opcode space when they decide to no longer support CS/DS/ES/SS segment prefixes. The space could be used for instructions that are the same in 32-bit and 64-bit modes. The primary ("first byte") opcode space is quite busy in 32-bit mode. Intel and AMD figured out a way to "hide" extra instruction prefixes in illegal modes of certain 16/32-bit instructions. Intel did this with the VEX prefix and AMD did it with the XOP prefix. The instructions they chose were LES/LDS and POP. This is the reason why some of the bits in those multi-byte prefixes have to be inverted, btw. Having 4 clean bytes available with no need for such silly games should prove useful in the future. The 4 string I/O instructions they suggest removing will be useful immediately. Removing all ring 3 I/O instructions (also part of the plan) will free up 8 further bytes in the primary opcode map for user space code. This could perhaps be used to provide shorter aliases of certain existing encodings -- so the instructions in question would still be available for kernels but applications would see better encoding density. And then there is the 67h byte being freed as well due to removing address size overrides. If they are sensible, they will also remove the BOUND instruction from 32-bit mode, but that is not in the current version of the plan. So what are the benefits? Free space in the primary opcode map => better encoding density... and they might not be doing this to give us shorter programs. They might be doing this so the parallel instruction decoders can handle more instructions per cycle. Getting rid of 16-bit data will make the data flow engine in future CPUs simpler (no more partial register stalls). They also get to remove lots and lots of special cases that undoubtedly cost engineering time and validation time.
muricula 3y ago
Looks like you will still be able to run 32 bit user mode applications under a 64 bit kernel. I'm not sure, but I think 32 bit guest kernels get the ax as well. " 3.3 Removal of 16-Bit and 32-Bit Protected Mode 16-bit and 32-bit protected mode are not supported anymore and cannot be entered. The CPU always operates in long mode. The 32-bit submode of Intel64 (compatibility mode) still exists. ... "
- jcranmer 3y ago
  > I'm not sure, but I think 32 bit guest kernels get the ax as well. This is somewhat beyond my knowledge of system programming, but my read is that it's just possible to support 32-bit guest kernels in the VM with some more emulation of the de-supported instructions. I don't know how many of those instructions already cause VM exits.
xorcist 3y ago
If I had to list one hundred ways x86 could be improved, not booting in 16-bit mode wouldn't be on it. It's just an incantation. There's no fallout from it. If we're talking firmware, the gigantic mess that used to be called ACPI, still leave users suffering every day for example.
- hinkley 3y ago
  I think that depends on if the existence of 16 bit mode has effects on IPC rates of the processor. If it's 2% of instruction cost, then kill it with fire. If it's raising the development cost by 1%, kill it with fire. If it's a fixed cost and isn't hurting anything, then meh.
  - userbinator 3y ago
    Unless they want to complete eliminate 16-bit operations, it won't matter. ...and eliminating 16-bit operations would be pure ideologically-driven stupidity, given how many classic RISCs with word-width-operations-only suffered greatly and the ones that survived (like ARM) evolved to add them back in.
    - jcranmer 3y ago
      What they're getting rid of is all of the extra fun memory management modes the x86 processor has, condensing everything down into just the paging mode with extremely gimped segment support that's all that's available in x86-64. That suggests to me that someone within Intel is thinking about basically rewriting the memory subsystem, where having to support all the fun things like real mode or virtual 8086 mode is much more painful. The 16-bit data operations are still around, with the 0x66 prefix, and even the ability to default a segment to not needing the 0x66 prefix to get 16-bit registers may still be around, though I'm not savvy enough on the retained features to say for certain. To be honest, there are two legacy x86 features which I suspect do have a noticeable tax on the support in the execution units: the x87 FPU stuff (due to the 80-bit floating-point types, and a variety of hardware-implemented transcendental instructions that need to be supported), and the legacy addressing modes.
AtlasBarfed 3y ago
Ok, so maybe you do that in boot order or some boot motdes. But ... remove it? There is SO MUCH silicon these days, honestly I think CPUs should start putting instruction set compatibility cores in, so you still dedicate .5% to a 16 bit compatibility core, 1% to the 32 bit mode, and maybe even an ARM mode. Honestly, since all CPUs are basically fronted by microcode, why can't modern CPU microcode be compatible with multiple instruction sets? Or provide some sort of programmable microcode section so emulators aren't done in software? While I'm bitching, what happened to actually running multiple OSes at once? I have like 16 cores, gigabytes of RAM, multiple display outputs ... why can't I actually run both Linux and Windows and OSX all at once without some bad virtualization container inside one overarching OS? Like, can't Intel manage that with chipset and CPU logic? Intel (and AMD) are DESPERATE to figure out things to get people to use all their extra cores and silicon for. Well, how about making multiple OS on the same machine an actually pleasant experience? Hell, I would love to run a smartphone OS as well.
- circuit10 3y ago
  > why can't modern CPU microcode be compatible with multiple instruction sets? Nvidia did something sort of similar to this, but couldn't get licensing to use x86. https://en.wikipedia.org/wiki/Project_Denver https://en.wikipedia.org/wiki/Project_Denver
- StillBored 3y ago
  why can't I actually run both Linux and Windows and OSX all at once without some bad virtualization container inside one overarching OS? Like, can't Intel manage that with chipset and CPU logic? Sounds like what you want is a LPAR or proper type 1 hypervisor, which despite everyone claiming to be type 1 none of them really are. And this is largely caused by the various device HW standards on the PC not natively supporting virtualization (or like nvidia charging extra for SRIOV functionality on their GPUs). So what happens is that all these hypervisors need something like VirtIo or hypervisor emulation of devices (ex e1000/ne2000, sb16, etc) to provide generic storage/networking/display/input devices on top of devices which don't themselves provide any virtualization support. Which in PC land is pretty much everything that doesn't support SRIOV. Which in turn means that a heavyweight OS +driver stack is required to manage the HW. So, you could build a PC based LPAR hypervisor. It would just be limited to the SRIOV capable devices, or plugging in piles of adapters, each one uniquely bound to a single partition. Ex: https://www.hitachi.com/rev/pdf/2012/r2012_02_104.pdf https://www.hitachi.com/rev/pdf/2012/r2012_02_104.pdf

by loeg 3y ago

KerrAvon 3y ago

The PDF goes into detail on this. tl;dr: > 16-bit and 32-bit protected mode are not supported anymore and cannot be entered. The CPU always operates in long mode. The 32-bit submode of Intel64 (compatibility mode) still exists.

dathinab 3y ago
Yes but there is a bit of a catcher due to some 32bit programs abusing certain instructions created for handling segmentation. And segmentation support will be partially removed. But no idea if the instruction in question will be gone.
- anticensor 3y ago
  Removed instructions and pseudocode of changing instructions are explicitly documented.

aforty 3y ago

It seemed pretty obvious to me from one of the graphics that they would remove 32-bit mode as well.

loeg 3y ago
> It seemed pretty obvious to me from one of the graphics that they would remove 32-bit mode as well. I don't believe it's that simple (or obvious, since you seem to be mistaken).
dathinab 3y ago
If you mean the graphics relatively at the beginning then no, they refer to boot phases and OS level stuff but that's not fully the same as what you need to run 32bit applications in a 64bit OS.

jcranmer 3y ago

> It's not clear to me if 32-bit mode would be axed as well, or if it would be retained (maybe partially). I've been reading the detailed pdf to see more details. It looks to me like 32-bit mode, specifically in the sense of a 32-bit distribution of modern software, is being retained. Segments would be converted more towards their 64-bit extremely attenuated mode, rather than the more robust functionality they have right now. So most 32-bit software shouldn't be affected, unless you're getting really dirty with the segmentation features or trying to support something like Win16.

peterfirefly 3y ago
> Segments would be converted more towards their 64-bit extremely attenuated mode, rather than the more robust functionality they have right now. Which, ten years down the line, should free up a bit more opcode space when they decide to no longer support CS/DS/ES/SS segment prefixes. The space could be used for instructions that are the same in 32-bit and 64-bit modes. The primary ("first byte") opcode space is quite busy in 32-bit mode. Intel and AMD figured out a way to "hide" extra instruction prefixes in illegal modes of certain 16/32-bit instructions. Intel did this with the VEX prefix and AMD did it with the XOP prefix. The instructions they chose were LES/LDS and POP. This is the reason why some of the bits in those multi-byte prefixes have to be inverted, btw. Having 4 clean bytes available with no need for such silly games should prove useful in the future. The 4 string I/O instructions they suggest removing will be useful immediately. Removing all ring 3 I/O instructions (also part of the plan) will free up 8 further bytes in the primary opcode map for user space code. This could perhaps be used to provide shorter aliases of certain existing encodings -- so the instructions in question would still be available for kernels but applications would see better encoding density. And then there is the 67h byte being freed as well due to removing address size overrides. If they are sensible, they will also remove the BOUND instruction from 32-bit mode, but that is not in the current version of the plan. So what are the benefits? Free space in the primary opcode map => better encoding density... and they might not be doing this to give us shorter programs. They might be doing this so the parallel instruction decoders can handle more instructions per cycle. Getting rid of 16-bit data will make the data flow engine in future CPUs simpler (no more partial register stalls). They also get to remove lots and lots of special cases that undoubtedly cost engineering time and validation time.

muricula 3y ago

Looks like you will still be able to run 32 bit user mode applications under a 64 bit kernel. I'm not sure, but I think 32 bit guest kernels get the ax as well. " 3.3 Removal of 16-Bit and 32-Bit Protected Mode 16-bit and 32-bit protected mode are not supported anymore and cannot be entered. The CPU always operates in long mode. The 32-bit submode of Intel64 (compatibility mode) still exists. ... "

jcranmer 3y ago
> I'm not sure, but I think 32 bit guest kernels get the ax as well. This is somewhat beyond my knowledge of system programming, but my read is that it's just possible to support 32-bit guest kernels in the VM with some more emulation of the de-supported instructions. I don't know how many of those instructions already cause VM exits.

xorcist 3y ago

If I had to list one hundred ways x86 could be improved, not booting in 16-bit mode wouldn't be on it. It's just an incantation. There's no fallout from it. If we're talking firmware, the gigantic mess that used to be called ACPI, still leave users suffering every day for example.

hinkley 3y ago
I think that depends on if the existence of 16 bit mode has effects on IPC rates of the processor. If it's 2% of instruction cost, then kill it with fire. If it's raising the development cost by 1%, kill it with fire. If it's a fixed cost and isn't hurting anything, then meh.
- userbinator 3y ago
  Unless they want to complete eliminate 16-bit operations, it won't matter. ...and eliminating 16-bit operations would be pure ideologically-driven stupidity, given how many classic RISCs with word-width-operations-only suffered greatly and the ones that survived (like ARM) evolved to add them back in.
  - jcranmer 3y ago
    What they're getting rid of is all of the extra fun memory management modes the x86 processor has, condensing everything down into just the paging mode with extremely gimped segment support that's all that's available in x86-64. That suggests to me that someone within Intel is thinking about basically rewriting the memory subsystem, where having to support all the fun things like real mode or virtual 8086 mode is much more painful. The 16-bit data operations are still around, with the 0x66 prefix, and even the ability to default a segment to not needing the 0x66 prefix to get 16-bit registers may still be around, though I'm not savvy enough on the retained features to say for certain. To be honest, there are two legacy x86 features which I suspect do have a noticeable tax on the support in the execution units: the x87 FPU stuff (due to the 80-bit floating-point types, and a variety of hardware-implemented transcendental instructions that need to be supported), and the legacy addressing modes.

AtlasBarfed 3y ago

Ok, so maybe you do that in boot order or some boot motdes. But ... remove it? There is SO MUCH silicon these days, honestly I think CPUs should start putting instruction set compatibility cores in, so you still dedicate .5% to a 16 bit compatibility core, 1% to the 32 bit mode, and maybe even an ARM mode. Honestly, since all CPUs are basically fronted by microcode, why can't modern CPU microcode be compatible with multiple instruction sets? Or provide some sort of programmable microcode section so emulators aren't done in software? While I'm bitching, what happened to actually running multiple OSes at once? I have like 16 cores, gigabytes of RAM, multiple display outputs ... why can't I actually run both Linux and Windows and OSX all at once without some bad virtualization container inside one overarching OS? Like, can't Intel manage that with chipset and CPU logic? Intel (and AMD) are DESPERATE to figure out things to get people to use all their extra cores and silicon for. Well, how about making multiple OS on the same machine an actually pleasant experience? Hell, I would love to run a smartphone OS as well.

circuit10 3y ago
> why can't modern CPU microcode be compatible with multiple instruction sets? Nvidia did something sort of similar to this, but couldn't get licensing to use x86. https://en.wikipedia.org/wiki/Project_Denver https://en.wikipedia.org/wiki/Project_Denver
StillBored 3y ago
why can't I actually run both Linux and Windows and OSX all at once without some bad virtualization container inside one overarching OS? Like, can't Intel manage that with chipset and CPU logic? Sounds like what you want is a LPAR or proper type 1 hypervisor, which despite everyone claiming to be type 1 none of them really are. And this is largely caused by the various device HW standards on the PC not natively supporting virtualization (or like nvidia charging extra for SRIOV functionality on their GPUs). So what happens is that all these hypervisors need something like VirtIo or hypervisor emulation of devices (ex e1000/ne2000, sb16, etc) to provide generic storage/networking/display/input devices on top of devices which don't themselves provide any virtualization support. Which in PC land is pretty much everything that doesn't support SRIOV. Which in turn means that a heavyweight OS +driver stack is required to manage the HW. So, you could build a PC based LPAR hypervisor. It would just be limited to the SRIOV capable devices, or plugging in piles of adapters, each one uniquely bound to a single partition. Ex: https://www.hitachi.com/rev/pdf/2012/r2012_02_104.pdf https://www.hitachi.com/rev/pdf/2012/r2012_02_104.pdf