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Comparing MTIA v1 vs Google Cloud TPU v4: MTIA v1's specs: The accelerator is fabricated in TSMC 7nm process and runs at 800 MHz, providing 102.4 TOPS at INT8

Comparing MTIA v1 vs Google Cloud TPU v4: MTIA v1's specs: The accelerator is fabricated in TSMC 7nm process and runs at 800 MHz, providing 102.4 TOPS at INT8 precision and 51.2 TFLOPS at FP16 precision. It has a thermal design power (TDP) of 25 W. Up to 128 GB of ram LPDDR5. Googles Cloud TPU v4: 275 teraflops (bf16 or int8), 90/170/192 W. 32 GiB of HBM2 RAM, 1200 GBps. From here: https://cloud.google.com/tpu/docs/system-architecture-tpu-vm#tpu_v4 https://cloud.google.com/tpu/docs/system-architecture-tpu-vm... So it seems that the Google Cloud TPU v4 has an advantage in terms of compute per chip and ram speed, but the Meta one is much more efficient (2x to 4x, it is hard to tell) and has more ram but it is slower ram?

innagadadavida 3y ago
Is there something that compares these to more consumer offering like Apple’s ANE?
- u017937387 3y ago
  [flagged]
benstrumental 3y ago
FWIW, you're comparing a training-specialized chip to an inference-specialized chip. It'd be more apples to apples to compare to TPU v4 lite, but I can't find that chip's details anywhere beyond some mentions in the TPU v4 paper: https://arxiv.org/abs/2304.01433 https://arxiv.org/abs/2304.01433
- KRAKRISMOTT 3y ago
  How does a training specialized chip function? Forward mode is simple, just a dot product machine. But how do you accelerate backprop on hardware? Does it have the vector Jacobian transformation lookup logic and table baked into hardware?
  - m00x 3y ago
    Look at the massive diff in the TDP & RAM to start with. Meta's is 1/3rd the TDP and has very different RAM.
  - dgacmu 3y ago
    Mostly you need to be able to stash intermediate products computed in the forward phase so that you can access them in the backward phase. This requires more memory, more memory bandwidth, more transpose, and also, training usually operates at slightly higher precision (bf16 instead of int8 as one example).
    - KRAKRISMOTT 3y ago
      What about the autodiff/VJP lookup table? What's the overhead like for those?
      - dgacmu 3y ago
        I think it's helpful to categorize the things that go into an ML accelerator as those that are big picture architectural - things like memory bandwidth and sizes, support for big operations like transposition, etc., -- and those that are fixed-function optimizations. In all of these systems, there's a compiler that's responsible for taking higher-level things and compiling them down to those low-level operations. And that includes the derivatives used in backprop - they just get mapped to the same plus a few more primitive operations. While there are few more fixed functions you need to add for loss functions and some derivatives, probably the largest difference is that you need to support transpose (and that you need all that extra memory & bandwidth to keep those intermediate products around in order to backprop on them) This paper has a nice summary of the challenges of going from an inference-only TPU to the inference-capable TPUv2: https://ieeexplore.ieee.org/document/9351692 https://ieeexplore.ieee.org/document/9351692 Look for the section "CHALLENGES AND OPPORTUNITIES OF BUILDING ML HARDWARE" But then things change more when you want to start supporting embeddings, so Google's TPUs have included a "sparse core" to separately handle those (the lookup and memory use patterns are drastically different from that of the typical dense matrix operations used for non-embedding layers) since TPUv2: https://arxiv.org/pdf/2304.01433.pdf https://arxiv.org/pdf/2304.01433.pdf

innagadadavida 3y ago

Is there something that compares these to more consumer offering like Apple’s ANE?

u017937387 3y ago
[flagged]

benstrumental 3y ago

FWIW, you're comparing a training-specialized chip to an inference-specialized chip. It'd be more apples to apples to compare to TPU v4 lite, but I can't find that chip's details anywhere beyond some mentions in the TPU v4 paper: https://arxiv.org/abs/2304.01433 https://arxiv.org/abs/2304.01433

KRAKRISMOTT 3y ago
How does a training specialized chip function? Forward mode is simple, just a dot product machine. But how do you accelerate backprop on hardware? Does it have the vector Jacobian transformation lookup logic and table baked into hardware?
- m00x 3y ago
  Look at the massive diff in the TDP & RAM to start with. Meta's is 1/3rd the TDP and has very different RAM.
- dgacmu 3y ago
  Mostly you need to be able to stash intermediate products computed in the forward phase so that you can access them in the backward phase. This requires more memory, more memory bandwidth, more transpose, and also, training usually operates at slightly higher precision (bf16 instead of int8 as one example).
  - KRAKRISMOTT 3y ago
    What about the autodiff/VJP lookup table? What's the overhead like for those?
    - dgacmu 3y ago
      I think it's helpful to categorize the things that go into an ML accelerator as those that are big picture architectural - things like memory bandwidth and sizes, support for big operations like transposition, etc., -- and those that are fixed-function optimizations. In all of these systems, there's a compiler that's responsible for taking higher-level things and compiling them down to those low-level operations. And that includes the derivatives used in backprop - they just get mapped to the same plus a few more primitive operations. While there are few more fixed functions you need to add for loss functions and some derivatives, probably the largest difference is that you need to support transpose (and that you need all that extra memory & bandwidth to keep those intermediate products around in order to backprop on them) This paper has a nice summary of the challenges of going from an inference-only TPU to the inference-capable TPUv2: https://ieeexplore.ieee.org/document/9351692 https://ieeexplore.ieee.org/document/9351692 Look for the section "CHALLENGES AND OPPORTUNITIES OF BUILDING ML HARDWARE" But then things change more when you want to start supporting embeddings, so Google's TPUs have included a "sparse core" to separately handle those (the lookup and memory use patterns are drastically different from that of the typical dense matrix operations used for non-embedding layers) since TPUv2: https://arxiv.org/pdf/2304.01433.pdf https://arxiv.org/pdf/2304.01433.pdf