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AMD originally intended Ryzen to have both x86 and ARM frontends, but the ARM frontend was cancelled after what we assume was the buyer[0] cancelled their order
by kmeisthax 3y ago
AMD originally intended Ryzen to have both x86 and ARM frontends, but the ARM frontend was cancelled after what we assume was the buyer[0] cancelled their order.
Dropping ARM usermode in the middle of an x86 host[1] would be particularly weird to build architecturally, though. You'd need x86 to correctly retain ARM register state and restore it, etc. The ARM side would also need architectural extensions to generate x86-side interrupts and syscalls for paravirtualization. You'd also need to be able to handle both AArch32 and AArch64 guests on an x86 host - and hopefully that host is in long mode, right!?
[0] There was speculation it might have been Amazon?
[1] "Host" in the most generic case of "software that controls the live-ness of other software": i.e. kernel, hypervisor, and/or emulator
- saagarjha 3y agoI feel like what you’d probably want to implement here are extensions that make it convenient to write high-performance translators.
- pavlov 3y agoMaybe something like Transmeta, where the instruction set was designed to act as a dynamic binary translation target: https://en.wikipedia.org/wiki/Transmeta https://en.wikipedia.org/wiki/Transmeta
- xattt 3y agoTransmets promised multiple architectures, but there was never a product demonstrated in the wild.
- pavlov 3y agoI think they demonstrated Sun picoJava support alongside x86, but no products actually shipped using this architecture: https://en.wikipedia.org/wiki/PicoJava https://en.wikipedia.org/wiki/PicoJava
- sgerenser 3y agoThis is essentially what Apple did with Apple Silicon to make Rosetta fast: https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-fast/ https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f... There’s a number of CPU features that make running translated x86 code much faster than it otherwise would be, like “Alternate Floating Point Mode” that happens to exactly match the x86’s floating point behavior.