Note that ram init in VisionFive 2 is done within u-boot SPL, which is loaded into cache-as-ram from the selected (microswitches on the board) boot device. The

Note that ram init in VisionFive 2 is done within u-boot SPL, which is loaded into cache-as-ram from the selected (microswitches on the board) boot device. The non-rewritable ROM inside the SoC does just take care of reading the microswitches and fetching u-boot SPL (or oreboot, an alternative early bootloader in the works). Remarkably, the boot selection can be UART. This small ROM has an XMODEM implementation for receiving the early bootloader. u-boot SPL does then check the microswitches again for where to fetch the next stage, which is usually opensbi with u-boot as bundled payload.